1. Field of the Invention
The present invention relates to a semiconductor integrated circuit configured to operate according to a multi-level digital signal and a test apparatus thereof, and particularly to a technique for providing stable operation of a power supply.
2. Description of the Related Art
In a case in which a semiconductor integrated circuit such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), memory, etc., which is provided using the CMOS (Complementary Metal Oxide Semiconductor) technology, is tested using a semiconductor test apparatus (which will be referred to as the “test apparatus” hereafter), the test apparatus supplies a test pattern to such a semiconductor integrated circuit, which is a device under test (which will be referred to as the “DUT” hereafter), so as to instruct the DUT to perform predetermined signal processing, and compares the data obtained as a result of the signal processing with an expected value, thereby performing quality judgment.
[Patent Document 1]
    International Publication WO 06/035604 pamphlet[Patent Document 2]    Japanese Patent Application Laid Open No. H11-74768[Patent Document 3]    Japanese Patent Application Laid Open No. 2004-125552[Patent Document 4]    Japanese Patent Application Laid Open No. 2004-125573
Upon receiving a test pattern, each flip-flop or each latch included in the DUT performs signal processing. In this state, current consumption occurs. On the other hand, when the signal processing is stopped, the circuit enters a static state, leading to reduction in the current consumption. Accordingly, in a case in which a test pattern is intermittently supplied to the DUT, current consumption by the DUT is also intermittent, and current flows in a burst manner. A power supply circuit arranged to supply power supply voltage to such a DUT is configured using a regulator. With an ideal power supply, such an arrangement is capable of supplying a constant power supply voltage regardless of the amount of the load current. However, in practice, such a power supply circuit has a significant output impedance, and has limited responsiveness to load changes. Accordingly, in a case in which the current consumption of the DUT changes in a burst manner, the power supply voltage changes according to the change in the current consumption of the DUT.
Such change in the power supply voltage has an effect on the operations of other circuit blocks included in the test apparatus, such as a pattern generator configured to generate a pattern signal to be supplied to the DUT, a timing generator configured to control the pattern transition timing, etc. This leads to a problem of jitter being superimposed on the signal thus generated.
If there is a block that operates intermittently in the internal circuit of the test apparatus, it leads to fluctuation in the power supply voltage to be supplied to such a block, which is also a problem.